Nordic Semiconductor (Mobile Semi) offers Ultra Low Power Data Retentional and Leakage
Ultra Low Power and Data Retention – Lowest power memory IP available on the market today.
Low Leakage. Each low voltage memory instance primarily uses low leakage HVT (LLHVT) devices and source biasing to minimize standby currents. Read and write assist circuits ensure reliable operation with a periphery power supply as low as 0.72V
Self biasing. Internal self-biasing capabilities provide ease of IP integration.
High Yield – Nordic requires the highest possible yield for their IC’s and memories are designed using statistical analysis techniques for yield and leakage.
Small Die Size – All Memories use proprietary design and layout techniques to achieve low power targets without increasing die size.
Memories Currently Available (qualified, silicon proven or in design phase).
| Part Number | Technology | Description |
| SP-ULL-GF22FDX | GF22FDX | Single port SRAM compiler with optional redundancy, low power retention mode, and three speed options |
| RF1P-ULL-GF22FDX | GF22FDX | Single port register file compiler with low power retention mode and three speed option |
| SP-LV-TS22 | TSMC N22ULL | Single port SRAM compiler with low power retention mode. Low leakage |
| SP-LVR-TS22 | TSMC N22ULL | Single port SRAM compiler with low power retention mode and column repair |
| SP-HS-TS22 | TSMC N22ULL | Single port SRAM compiler with low power retention mode. High speed, pins on side |
| ROM-ULV-TS22 | TSMC N22ULL | VIA programmable ROM with differential bit cell |
| RF1P-HS-TS22 | TSMC N22ULL | Single port register file compiler with low power retention mode |
| RF2P-HS-TS22 | TSMC N22ULL | Two port register file (1R1W) with low power retention mode |
| SP-HSLV-TS40ULP | TSMC N40ULP | Single port SRAM compiler with low power retention mode |
| SP-LV-TS55EF | TSMC 55 with embedded flash | Single port SRAM compiler with low power retention mode |
| SP-HSLV-TS55EF | TSMC 55 with embedded flash | Single port SRAM compiler with low power retention mode |
| SP-HD-TA180 | TSMC 180nm mixed signal 3v | Single port SRAM compiler using logic rules |
| ROM-HD-TA180 | TSMC 180nm mixed signal 3v | VIA programmable ROM |
| SP-HD-TA180-BCD | TSMC 180nm BCD | Single port SRAM compiler using logic rules |
| ROM-HD-TA180-BCD | TSMC 180nm BCD | VIA programmable ROM |
| SP-HD-TA180-MSD | TSMC 180nm mixed signal 5v | Single port SRAM compiler using logic rules |
| ROM-HD-TA180-MSD | TSMC 180nm mixed signal 5v | VIA programmable ROM |